Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
SystemVerilog (IEEE 1800 standard) is rapidly getting popular amongst design and verification community as a language of choice for describing the digital circuits. Recently, SystemVerilog is also extended to account for modeling for analog/mixed-signal circuits. These extensions allow users to model analog/mixed-signal behavior more accurately and support their evaluation by discrete event driven simulators. Specifically, these extensions allow creation and use of a SystemVerilog real signal that can support bi-directional communication. While such SystemVerilog real signal representations can be used to effectively model of analog mixed-signal behavior, these representations fall short in addressing issues in real life design applications.
The growing amount of analog circuitry on today's SoCs (System on Chip) further cements the growing understanding that isolated analog and digital verification may no longer be sufficient to reach tapeout. What is often needed is a chip-level functional verification that examines the functional interactions between analog and digital blocks. The challenges lie in how to implement such tasks, especially given that a SPICE/RTL (register-transfer level) co-simulation may be too slow. Verilog, for instance, has very limited real number modeling (RNM) support in that engineers may use real variables inside a model, but there are no real variable ports. VHDL (VHSIC Hardware Description Language or Very High Speed Integrated Circuit Hardware Description Language), on the other hand, supports real number ports, has custom or compound signals and ports that make it possible to pass both current and voltage, and offers custom resolution functions. The issue is that Verilog is nonetheless far more widely used for digital design than VHDL. Verilog-AMS (VAMS) is widely used for RNM. VAMS supports real number ports and variables, along with six resolution functions on wreal nets. VAMS also has an analog solver if higher accuracy is desired, along with a discrete solver that may be used for real value equations. SystemVerilog, meanwhile, is making strong inroads into digital design and verification. Far more than just another version of Verilog, SystemVerilog also includes extensive verification features and an assertion language. But the 2009 Language Reference Manual (LRM) does very little for analog modeling. For example, SystemVerilog provides a real variable that may be used as a port. Nonetheless, by its definition as variable, the port cannot be bi-directional, cannot have multiple drivers, and so forth. Real number modeling provides a fast way to run a chip-level simulation with analog values, but the support for RNM in the current SystemVerilog Language Reference Manual (2009 LRM) is unfortunately very limited.
Thus, there exists a need for a method, a system, and an article of manufacture for implementing analog behavioral modeling and IP (intellectual property) integration using SystemVerilog Hardware Description Language.